1. Field of the Invention
The present invention relates to a data processing apparatus and method, and in particular to techniques for handling write transactions in a data processing apparatus.
2. Description of the Prior Art
A data processing apparatus may comprise a plurality of devices interconnected by bus circuitry. Data is transferred between the devices via the bus circuitry. One particular type of transfer that may take place is referred to as a write transaction, which is generated by a bus master, and issued via the bus circuitry to a destination bus slave. When generating a write transaction, the bus master will generate a write address identifying an address in memory at which the data the subject of the write transaction should be written, and will separately generate the write data to be written at that address. The write address will be transferred over the bus circuitry separately to the write data.
The devices within the data processing apparatus will either have a bus master interface, a bus slave interface, or both, dependent on whether those devices are to act as bus masters, bus slaves, or both bus masters and bus slaves (dependent on the transaction).
Considering a write transaction, it will be appreciated that the bus slave responsible for storing the write data at the address specified by the write address will need to have received the write address before it can take steps to store the write data. Accordingly, known protocols used to define how signals should be transferred over the bus circuitry typically require that the write address is presented at an interface at the same time or before the actual write data associated with that write address.
As the design of such bus circuitry increases in complexity, some variations can occur in the speed with which a write address and its associated write data are transferred over the various connection paths provided by the bus circuitry, and accordingly it is typically required to provide logic at the various interfaces to perform any necessary re-alignment of the write data and the write address to ensure that the above protocol requirement is met.
It is an object of the present invention to provide an improved data processing apparatus which enables more efficient handling of write transactions.